Elevated pocket pixels, imaging devices and systems including the same and method of forming the same

ABSTRACT

An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for additional absorption. In addition, the elevated photosensors reduce the size of the pixel cells while reducing leakage, image lag, and barrier problems.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to application Ser. No. 11/300,378, filed onDec. 15, 2005, the disclosure of which is hereby incorporated byreference herein in its entirety.

BACKGROUND OF THE INVENTION

Solid state image sensors are increasingly being used in a wide varietyof imaging applications as low cost imaging devices. One such imagesensor is a CMOS image sensor. A CMOS image sensor includes a focalplane array of pixel cells. Each cell includes a photosensor, photogate,photoconductor, or photodiode having an associated charge accumulationregion within a substrate for accumulating photo-generated charge. Eachpixel cell may include a transistor for transferring charge from thecharge accumulation region to a floating diffusion region, and atransistor for resetting the floating diffusion region to apredetermined charge level. The pixel cell may also include a sourcefollower transistor for receiving and amplifying charge from thefloating diffusion region and an access transistor for controlling thereadout of the cell's contents from the source follower transistor.

Accordingly, in a CMOS image sensor, the active elements of a pixel cellperform the necessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion region accompanied by charge amplification; (4) resetting thefloating diffusion region to a known state; (5) selection of a pixelcell for readout; and (6) output and amplification of a signalrepresenting pixel cell stored charge from the floating diffusionregion.

CMOS image sensors of the type discussed above are as discussed in Nixonet al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEEJournal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); andMendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions onElectron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat.Nos. 6,177,333 and 6,204,524, assigned to Micron Technology, Inc., whichdescribe the operation of CMOS image sensors, and the contents each ofwhich are incorporated herein by reference.

In a CMOS image sensor having photodiodes as the photosensors, whenincident light strikes the surface of a photosensor, electron/hole pairsare generated in a p-n junction of the photosensor. The generatedelectrons are collected in the n-type region of the photosensor. Thephoto charge moves from the initial charge accumulation region to thefloating diffusion region or the charge may be transferred to thefloating diffusion region via a transfer transistor. The charge at thefloating diffusion region is typically converted to a pixel outputvoltage by a source follower transistor.

CMOS image sensors may have difficulty transferring all of thephotogenerated charge from the photosensor to the floating diffusionregion. One problem with transferring charge occurs when the n-typesilicon layer of the photosensor is located close to the surface; thiscauses electron/carrier recombination due to surface defects. There is aneed to reduce this electron/carrier recombination to achieve goodcharge transfer to the floating diffusion region. Another obstaclehindering “complete” charge transference includes potential barriersthat exist at the gate of the transfer transistor.

Additionally, known CMOS image sensors provide only approximately afifty percent fill factor, meaning only half of the pixel cell isutilized in converting light to charge carriers. As shown in FIG. 1,only a small portion of the pixel cell 100 is occupied by thephotosensor 110 (e.g., a photodiode). The remainder of the cell 100includes the floating diffusion region 120, coupled to a transfertransistor gate 170, and source/drain regions 140 for reset, sourcefollower, and row select transistors having respective gates 130, 150,and 160. It is desirable to increase the fill factor of the cell 100.

Image sensors may utilize a pixel cell containing a p-n-p photodiodephotosensor 110 as is shown in FIG. 2, which is a cross-sectional viewof the pixel cell 100 of FIG. 1, taken along line A-A′. The pixel cell100 shown in FIG. 2 has a p-type substrate 235 with a p-well 225 formedtherein. In the illustrated example, a p-type region 205 of photosensor110 is located closest to the surface of substrate 235 and an n-typeregion 215 is buried beneath the p-type region 205. The p-n-p photodiodephotosensor 110 has some drawbacks. First, there can be a lag problemsince the pixel cell 100 uses a transfer transistor gate 170 fortransferring charge to the floating diffusion region 120. Lag occursbecause during integration the electron carriers are collected in thesandwiched n-type region 215 and then transferred to the floatingdiffusion region 120 through the transfer transistor gate 170. In orderto fully utilize the generated electron carrier, it is necessary toeliminate two energy barriers to reach the floating diffusion region 120(i.e., there is one barrier between the photosensor 110 and the transfertransistor gate 170 and another barrier between the transfer transistorgate 110 and floating diffusion region 120).

Charge leakage is another problem associated with the conventional p-n-pphotodiode photosensor 110. One source of such leakage occurs when thetransfer transistor gate 170 length is too short, causing sub-thresholdcurrent to become significantly high due to charge breakdown betweenn-type regions on both sides of the transfer transistor gate channel.

Additionally, as the total area of pixel cells continues to decrease(due to desired scaling), it becomes increasingly important to createhigh sensitivity photosensors 110 that utilize a minimum amount ofsurface area. Raised photosensors 110′, as shown in FIG. 2A, have beenproposed as a way to increase the fill factor and optimize thesensitivity of a CMOS pixel cell 100′ by increasing the sensing area ofthe cell 100′ without increasing the surface area of the substrate 235.Further, the raised photosensor 110′ increases the quantum efficiency ofthe cell 100′ by bringing the sensing region closer to the microlens(not shown) used to focus light on the photosensor 110′. However, raisedphotosensors 110′ also have problems with leakage current across theirelevated p-n junctions. Accordingly, a raised photosensor 110′ thatreduces this leakage, while increasing the quantum efficiency of thepixel cell 100′, is desired.

Moreover, referring to FIGS. 2 and 2A, in CMOS image sensors, electronsare generated by light incident on the photosensor 110, 110′ and arestored in the n-type region 215, 215′. These charges are transferred tothe floating diffusion region 120 by the transfer transistor gate 170when the transfer transistor gate 170 is activated. The source followertransistor (FIG. 1) produces an output signal based on the transferredcharges. A maximum output signal is proportional to the number ofelectrons extracted from the photosensor 110, 110′. However, a certainamount of incident light is not absorbed by the photosensor 110, 110′,but, is instead reflected from its surface and lost. The loss of thisincident light decreases responsivity, dynamic range and quantumefficiency of the image sensor.

Accordingly, it is desirable to have a raised photosensor that bettercaptures reflected incident light and directs the reflected light to thephotosensor so that more of the light is absorbed and detected.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a prior art image sensor/pixel cell.

FIG. 2 is a cross-sectional view of a prior art pixel cell andphotosensor.

FIG. 2A is a cross-sectional view of a prior art pixel cell and raisedphotosensor.

FIG. 3 is a block diagram of an embodiment discussed herein.

FIG. 4 is a cross-sectional view of an embodiment of a portion of theFIG. 3 photosensor.

FIG. 4A is a cross-sectional view of another embodiment discussedherein.

FIG. 4B is a cross-sectional view of another embodiment discussedherein.

FIG. 4C is a cross-sectional view of another embodiment discussedherein.

FIG. 4D is a cross-sectional view of another embodiment discussedherein.

FIG. 5A is a cross-sectional view of another embodiment at an initialstage of processing.

FIG. 5B illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5A.

FIG. 5C illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5B.

FIG. 5D illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5C.

FIG. 5E illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5D.

FIG. 5F illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5E.

FIG. 5G illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5F.

FIG. 5H illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5G.

FIG. 5I illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5H.

FIG. 5J illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5I.

FIG. 5K illustrates the embodiment of FIG. 5A at a stage of processingsubsequent to that shown in FIG. 5J.

FIG. 6A is a cross-sectional view of an embodiment of the pixel cell ofFIG. 4 during an initial stage of processing.

FIG. 6B illustrates the embodiment of FIG. 6A at a stage of processingsubsequent to that shown in FIG. 6A.

FIG. 6C illustrates the embodiment of FIG. 6A at a stage of processingsubsequent to that shown in FIG. 6B.

FIG. 6D illustrates the embodiment of FIG. 6A at a stage of processingsubsequent to that shown in FIG. 6C.

FIG. 6E illustrates another embodiment discussed herein.

FIG. 7 is a block diagram of a CMOS imager chip having an array of pixelcells.

FIG. 8 is a schematic drawing of a processing system employing a CMOSimager having elevated photosensors constructed in accordance with anembodiment discussed herein.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof and illustrateembodiments that may be practiced. It should be understood that likereference numerals represent like elements throughout the drawings.These embodiments are described in sufficient detail to enable thoseskilled in the art to practice them, and it is to be understood thatother embodiments may be utilized, and that structural, logical andelectrical changes may be made.

The term “substrate” is to be understood as includingsilicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology,doped and undoped semiconductors, epitaxial layers of silicon supportedby a base semiconductor foundation, and other semiconductor structures.Furthermore, when reference is made to a “substrate” in the followingdescription, previous process steps may have been utilized to formregions or junctions in the base semiconductor structure or foundation.In addition, the semiconductor need not be silicon-based, but could bebased on silicon-germanium, germanium, gallium arsenide, or othersemiconductor material, for example.

The term “pixel” or “pixel cell” refers to a picture element unit cellcontaining a photosensor and transistors for converting light radiationto an electrical signal. For purposes of illustration, a representativepixel cell is illustrated in the figures and the description herein and,typically, fabrication of all pixel cells in an imager pixel array willproceed simultaneously in a similar fashion. Moreover, while afour-transistor pixel cell is described, the embodiments are not limitedto a four transistor configuration. The embodiments may be employed withany suitable electrical pixel cell architecture, such as two-transistor,three-transistor, five- or more transistor pixel cells.

In the following description, the embodiments are described in relationto a CMOS image sensor for convenience purposes only; furtherembodiments, however, have wider applicability to any photosensor of anyimage sensor such as charge-couple devices (CCD). Now referring to thefigures, FIG. 3 illustrates a pixel cell 300 constructed in accordancewith a first embodiment. From the top plan view of the pixel cell 300, araised photosensitive region 490 (described in more detail below) andcell insulation region 330 can be seen. The fill factor of the cell 300is nearly 100 percent, as the photosensitive region 490 covers theentire surface area of the cell 300. Although FIG. 3 shows the raisedphotosensitive region 490 as covering the entire pixel cell 300, theraised photosensitive region 490 could have a smaller surface area andcould cover much less of pixel cell 300, if desired. Also shown in FIG.3 is cell insulation region 330 surrounding the raised photosensitiveregion 490 so as to insulate the pixel cell 300 from other cells and/orcircuitry when the cell 300 if part of an array or image sensor.Alternatively, isolation trenches or regions (not shown) may be formedin the raised photosensitive region 490 to provide isolation of theraised photosensitive region 490 from raised portions of adjacent cells.Also shown in FIG. 3 are transfer transistor gate 320, source followertransistor gate 340, row select transistor gate 350 and reset transistorgate 360. It should be noted that upper electrode layer 471 (describedbelow) is not illustrated in FIG. 3 to allow the plan view illustrationof pixel cell 300 to show photosensitive region 490.

FIG. 4 illustrate cross-sectional views of different embodiments of thepixel cell 300, taken along line B-B′ of FIG. 3. Referring to FIG. 4, aphotosensor 420 having a doped region 430 is formed in a substrate 410.The photosensor 420 is a photodiode and may be a pinned p-n-p, n-p-n,p-n or n-p junction photodiode, a Schottky photodiode, or any othersuitable photodiode. For illustrative purposes only, the photosensor 420is an n-p photodiode, and substrate 410 is a p-type substrate.

FIG. 4 also illustrates a floating diffusion region 440 and shallowtrench isolation (STI) regions 470 in the substrate 410. A drain region450 is also formed in the substrate 410. Other structures of pixel cell300 include a transfer transistor gate 320, and reset transistor gate360 having a similar gatestack as that of the transfer transistor gate320.

As shown in FIG. 4, substrate 410 has a first surface level 480. Anepitaxial layer 485 is grown from the top of this first surface level480 to a second surface level 495. Above the epitaxial layer 485 is ahydrogenated amorphous silicon layer 310 for the photosensitive region490. As used herein, the term “hydrogenated amorphous silicon” meanseither conventional hydrogenated amorphous silicon (represented a-Si:H)or deuterated amorphous silicon (represented a-Si:D), having deuteriumsubstituted for hydrogen.

The epitaxial layer 485 and the hydrogenated amorphous siliconphotosensitive region 490 are doped such that they have opposite dopingtypes to create a p-n junction above the surface level 480 of thesubstrate 410. This creates, in effect, an elevated or raisedphotosensitive region 490. In FIG. 4, the epitaxial layer 485 is dopedp-type, creating a p-n junction with the n-type surface region 430.Accordingly, the hydrogenated amorphous silicon photosensitive region490 is doped n-type. There are several advantages of having an elevatedphotosensitive region 490 constructed in accordance with the illustratedembodiment such as increasing the fill factor and optimizing thesensitivity of the pixel cell 300 by increasing the sensing area of thecell 300.

Photosensitive region 490 does not have a planar upper surface allowingfor an even higher fill factor and further increasing the quantumefficiency of the raised photosensitive region 490. In knownphotosensors, which have a planar upper surface, some of the incidentlight is absorbed by the photosensors, however, some of the incidentlight is reflected off the surface of the photosensors. The raisedphotosensitive region 490 of the illustrated embodiment has, instead, anupper surface profile which provides slanted or curved sidewalls 491capable of directing light reflected off one portion of the raisedphotosensitive region 490 to another portion for the photosensitiveregion 490 for capture. In the FIG. 4 embodiment, the upper surface 494has an indentation, pocket or trench having side walls 491, shown ingreater detail in FIG. 4A, which is an expanded cross-sectional view ofthe raised photosensitive region 490 of FIG. 3. It should be appreciatedthat while FIG. 4 shows a flat-bottomed trench 492, it may also have arounded bottom or v-shaped bottom.

As shown in FIG. 4A, raised photosensitive region 490 has a u-shapedcross-sectional profile; however, other cross-sectional profiles, e.g.,a v-shaped profile (FIG. 4C described below) or similar u-shapedconfiguration (FIG. 4D described below), may also be used. In theillustrated embodiment, raised photosensitive region 490 comprises anupper electrode layer 471 (e.g., transparent such as ITO) above ahydrogenated amorphous silicon layer 490 above a metal conductive layer481. Each layer is configured to contour to the indentation shape ofphotosensitive region 490.

With the u-shaped configuration illustrated in FIG. 4A, any light thatis reflected off the surface of the raised photosensitive region 490 isredirected to another location on the raised photosensitive region 490to have another chance at being absorbed. If light is not absorbed atthat location, it may be reflected again and redirected to anotherlocation on the raised photosensitive region 490 to have yet anotherchance at being absorbed. Multiple redirection of reflected light mayoccur in any embodiment described herein. It should also be appreciatedthat a pixel cell 300 can have a series of photosensitive regions andthus, having a series of u-shaped photosensitive regions, as illustratedin FIG. 4B, having an effective area “d” determined by the desired lightwavelength of the light to pass through, for example, red, green or bluelight.

FIG. 4C is an expanded cross-section view of another embodiment, whereinthe raised photosensitive region 490′ has a v-shaped trenchconfiguration. Again, sidewalls 491′ are provided in the upper surfaceprofile of photosensitive region 490′ capable of redirecting reflectedlight from one portion of the photosensitive region to another.

FIG. 4D is an expanded cross-sectional view of another embodiment,wherein the photosensitive region 490″ has another u-shaped trenchconfiguration. This configuration removes a portion of the metal layer481 by any known etching process. It should be appreciated that whileFIG. 4D shows a flat-bottomed trench, it may also have a rounded bottomor a v-shaped bottom. The various shapes, trenches and configurationsmay be obtained by selecting different methods of masking and/or etchingas is known in the art. In particular, the various shapes, trenches andconfigurations can be formed using a host of dry or wet etch techniquesincluding isotropic/anisotropic etching methods or deep dry etchingtechniques. The walls can also be sloped using wet isotropic etches.

It should be appreciated that necessary isolation implants can also beperformed. It should also be appreciated that the trenches, pockets orindentations can be of varying depths if necessary for different colorsto maximize the efficiency of light collection and the effective areas“d,” as shown back in FIG. 4B, are kept the same as the known raisedphotosensitive region. In another embodiment, the trench can vary indepth to optimize red collection or, in one other embodiment, the blueand green photosensitive regions have a planar surface while the redphotosensitive region has indentation features as described herein.

Generally, a photosensitive region according to the embodimentsdescribed herein has a greater signal-to-noise ratio than a prior artphotosensitive region. However, there may still be some scatter due to aminimal amount of incident light that is never absorbed by thephotosensitive region of the embodiments described herein. For instance,a photosensitive region having a u-shaped configuration has a greatersurface area than a photosensitive region having a v-shapedconfiguration, however a u-shaped configuration may have a tendency toscatter a greater amount of light to neighboring pixels. Therefore,dimensions and spacing of both u- and v-shaped configurations may beselected to increase surface area for photon capture and minimizescatter. In the case of a v-shaped configuration, reflecting surfacesare preferably located so that any scattered light will go toneighboring pixels that are not being read at the same time, therebyminimizing optical cross-talk.

Although photosensitive region 490 of FIG. 3 is shown to have a singleindentation or trench, it should be noted that the embodiments are notso limited. It should be appreciated that a photosensitive region havingsidewalls with a pitch greater than ¼ the wavelength of light issuitable.

FIG. 5A shows another embodiment of pixel cell 300 at an initial stageof fabrication. In a p-type substrate 410, a separate p-well 460 isformed therein. Multiple high energy implants may be used to tailor theprofile and position of the p-type well 460; typically, the p-wellregion 460 will have a higher dopant concentration than the p-typesubstrate 410. A floating diffusion region 440 is formed in the p-well460, and is doped n-type in this embodiment.

Isolation regions 470 are etched into the surface of the substrate 410,by any suitable method or technique, and are filled with an insulatingmaterial to form STI isolation regions. The isolation regions 470 may beformed either before or after formation of the p-well 460. A photosensor420 is formed, in this embodiment, by creating a n-type region 430 inthe p-type substrate 410. Photosensor 420 is not, however, limited to ann-p design and may be any suitable type of photosensor.

Also shown in FIG. 5A, a transfer transistor gate 320 and a resettransistor gate 360 are formed at the surface of the substrate 410between the photosensor 420 and floating diffusion region 440. Thetransfer and reset transistor gates 320, 360 include an insulating oroxide layer 510 over a conductive layer 520 formed over a gate oxidelayer 530 at the surface of the substrate 410. Preferably, theconductive layer 520 comprises a silicide or silicide/metal alloy. Theselayers 510, 520, 530 may, however, be formed of any suitable materialusing any suitable method. Completion of the transistor gates 320, 360includes the addition of oxide spacers 515 on at least one side of thetransistor gatestacks. The spacers 515 may be formed of any suitablematerial, including, but not limited to silicon dioxide. As desired,other transistor gates may be erected simultaneously with transfertransistor gate 320 and reset transistor gate 360 during this step, andmay or may not contain the same layer combinations as these gate stacks.

Referring to FIG. 5B, a boron doped phosphosilicate glass (BPSG) layer810 is deposited over substrate 410. Then, a contact 820 is formed toexpose photosensor 420 as shown in FIG. 5C. Contact 820 can be formedusing any etch method known in the art. A metal layer 830, e.g.,Tungsten, is deposited to fill contact 820, as shown in FIG. 5D, andthen, metal layer 830 is planarized using e.g., chemical mechanicalpolishing (CMP). Referring to FIG. 5E, a first metal interconnect 860 isformed above metal layer 830 and layer 810. A interlevel dielectriclayer (ILD) 840, as shown in FIG. 5F, is patterned above first metalinterconnect layer 860 and layer 810. ILD layer 840 comprises an oxidein this embodiment, however, it should be appreciated that ILD layer 840should not be so limited.

Still referring to FIG. 5F, vias 850 are formed in the ILD layer 840.Each via 850 can be formed using any etch method known in the art. InFIG. 5G, second metal interconnect layer 870 is formed to fill the vias850 and above ILD layer 840. The second metal interconnect layer 870, inthis embodiment, is aluminum. It should be appreciated, however, thatsecond metal interconnect layer 870 can be any type of metal layer knownin the art.

Referring to FIG. 5H, a second ILD layer 880 is deposited above secondmetal interconnect layer 870 and ILD layer 840. The second ILD layer 880in this embodiment comprises an oxide, however, similar to ILD layer840, it should not be so limited. In FIG. 5I, ILD layer 880 is etchedusing any method known in the art to form the indentation shapesdescribed above. Then in FIG. 5J, a third metal interconnect layer 890(same as layer 481 in FIGS. 4A-4C) is formed above ILD layer 880. Thethird metal interconnect layer 890 is then patterned and etched. In FIG.5K, a hydrogenated amorphous silicon layer 891 and a top electrode layer892 are deposited above the third metal interconnect layer 890. Thedescribed process flow can also be used to fabricate the embodiments ofFIGS. 4B-4D.

At this stage, the formation of the pixel cell 300 (FIG. 5K) isessentially complete. Additional processing steps may be used to formadditional insulating, shielding, and metallization layers as desired(described in more detail below).

FIG. 6A shows another embodiment of a pixel cell 300 at an initial stageof fabrication. In a p-type substrate 410, a separate p-well 460 isformed therein. Multiple high energy implants may be used to tailor theprofile and position of the p-type well 460; typically, the p-wellregion 460 will have a higher dopant concentration than the p-typesubstrate 410. A floating diffusion region 440 is formed in the p-well460, and is doped n-type in this embodiment.

Isolation regions 470 are etched into the surface of the substrate 410,by any suitable method or technique, and are filled with an insulatingmaterial to form STI isolation regions. The isolation regions 470 may beformed either before or after formation of the p-well 460. A photosensor420 is formed, in this embodiment, by creating a n-type region 430 inthe p-type substrate 410. Photosensor 420 is not, however, limited to ann-p design and may be any suitable type of photosensor.

Also shown in FIG. 6A, a transfer transistor gate 320 and a resettransistor gate 360 are formed at the surface of the substrate 410between the photosensor 420 and floating diffusion region 440. Thetransfer and reset transistor gates 320, 360 include an insulating oroxide layer 510 over a conductive layer 520 formed over a gate oxidelayer 530 at the surface of the substrate 410. Preferably, theconductive layer 520 comprises a silicide or silicide/metal alloy. Theselayers 510, 520, 530 may, however, be formed of any suitable materialusing any suitable method. Completion of the transistor gates 320, 360includes the addition of oxide spacers 515 on at least one side of thetransistor gatestacks. The spacers 515 may be formed of any suitablematerial, including, but not limited to silicon dioxide. As desired,other transistor gates may be erected simultaneously with transfertransistor gate 320 and reset transistor gate 360 during this step, andmay or may not contain the same layer combinations as these gate stacks.

Referring now to FIG. 6B, a selective epitaxial layer 485 is grown nearthe surface of the substrate 410, over the photosensor 420 and adjacentthe sidewall 516 of spacer 515 of the transfer transistor gate 320. Theepitaxial layer 485 is grown over this selected region using a hardmask, for example, a nitride film, to cover other regions of thesubstrate 410 such as the floating diffusion region 440. By performing achemical vapor deposition process, the epitaxial layer 485 may be formedusing any suitable precursor (e.g., silicon tetrachloride, silane, anddichlorosilane). In addition, the epitaxial layer 485 can be doped aseither n-type or p-type by the addition of a suitable dopant gas intothe deposition reactants. In the illustrated embodiment, the epitaxiallayer 485 is doped p-type, to create a p-n junction at the intersectionof the epitaxial layer 485 with the surface layer 430. The epitaxiallayer 485 is planarized using CMP to a height of about 500-1000Angstroms above the surface of the substrate. An oxide cap 560 may beused to cover gate stacks 320, 360 to act as a CMP stop.

Subsequently, as shown in FIG. 6C, a buffer layer 570 (e.g., TEOS orBPSG) is deposited over the entire substrate 410. An opening 580 is thenpatterned in the layer 570 above the photosensor 420 in the substrate410.

Referring now to FIG. 6D, hydrogenated amorphous silicon is deposited tofill the opening 580 and to cover the buffer layer 570, creating a layer310 being for the raised photosensitive region 490 (FIG. 4). The layer310 is then planarized to a thickness of about 500-1000 Angstroms toreform the indentation. A top electrode layer 471 is deposited abovelayer 310. A color filter array 590 can then be formed above topelectrode layer 471, followed by a microlens 595 being formed abovecolor filter array 590. It should be appreciated that a secondhydrogenated amorphous silicon layer (not shown) may also be depositedon top of layer 310. It should also be appreciated that a metalconductive layer 481, as illustrated in FIGS. 4A, 4C and 4D, can beblanket deposited to cover the buffer layer 570 before depositinghydrogenated amorphous silicon layer 310 and top electrode layer 471, ifdesired. The metal conductive layer 481 would then be planarized usingCMP to reform an indentation (opening 580).

Oppositely doping layers 310 and 471, respectively p-type and n-type,will create an additional p/n junction raised above the photosensor 420.Alternatively, the two amorphous silicon layers may be doped the sametype (either n-type or p-type depending on the dopant used for thesurface region 430 and epitaxial region 485) as to create effectivelyone layer. The concentration levels of dopants may be similar to that ofa conventional photodiode. Using conventional masking techniques, theamorphous silicon layer can be patterned as desired. It should beappreciated that the resulting raised photodiode structure 599 can beimplemented as a plurality of photodiode structures or an array, asshown in FIG. 6E, each respective structure being for red light (R),blue light (B), or green light (G).

At this stage, the formation of the pixel cell 300 (FIG. 4) isessentially complete. Additional processing steps may be used to forminsulating, shielding, and metallization layers as desired. For example,an inter-level dielectric (ILD) such as insulating layer 370 (FIG. 3)may be formed to provide adequate insulation between metallized layersas well as to isolate the amorphous silicon layer 310 of a pixel cell300 from adjacent pixel cells. Because an increased percentage of eachpixel cell is covered by photo-sensing material in accordance with thisembodiment, transparent metallization layers may be used, so that lightis not blocked from the photosensor. Conventional layers of conductorsand insulators (not shown) may also be used to interconnect thestructures and to connect the pixel to peripheral circuitry.

The described and illustrated embodiment above utilizes a silicon typesubstrate 410. Alternatively, it may be implemented as a SOI (silicon oninsulator) design, utilizing any suitable insulating layer sandwichedbetween the substrate and an additional silicon layer. The other waferstructures discussed previously, such as SOS and germanium substrates,may also be used.

FIG. 7 illustrates a block diagram of an image sensor 610 having a pixelarray 640 with each pixel cell being constructed as in one of theembodiments described above. Pixel array 640 comprises a plurality ofpixels arranged in a predetermined number of columns and rows (notshown). Attached to the array 640 is signal processing circuitry, asdescribed herein, at least part of which may be formed in the substrate.The pixels of each row in array 640 are all turned on at the same timeby a row select line, and the pixels of each column are selectivelyoutput by respective column select lines.

A plurality of row and column lines are provided for the entire array640. The row lines are selectively activated by a row driver 630 inresponse to row address decoder 620. The column select lines areselectively activated by a column driver 660 in response to columnaddress decoder 670. Thus, a row and column address is provided for eachpixel. The CMOS image sensor is operated by the timing and controlcircuit 650, which controls address decoders 620, 670 for selecting theappropriate row and column lines for pixel readout. The control circuit650 also controls the row and column driver circuitry 630, 660 such thatthese apply driving voltages to the drive transistors of the selectedrow and column lines.

The pixel column signals, which typically include a pixel reset signal(V_(rst)) and a pixel image signal (V_(sig)), are read by a sample andhold circuit 680 associated with the column device 660. V_(rst) is readfrom a pixel immediately after the floating diffusion region 440 isreset out by the reset transistor gate 360; V_(sig) represents thecharges transferred by the transfer transistor gate 320, from thephotosensitive regions 420, 490 to the floating diffusion region. Adifferential signal (V_(rst)−V_(sig)) is produced by differentialamplifier 690 for each pixel which is digitized by analog to digitalconverter 695 (ADC). The analog to digital converter 695 supplies thedigitized pixel signals to an image processor 685 which forms a digitalimage.

FIG. 8 shows a system 700, which includes an image sensor 610constructed in accordance with an embodiment described above. The system700 may be part of a digital camera, which may be a digital, still orvideo camera 701, other camera or other imaging system. The image sensor610 may receive control or other data from system 700. System 700includes a processor 720 or a central processing unit (CPU) for imageprocessing, or other image handling operations. The processor 720communicates with various devices over a bus 710. Some of the devicesconnected to the bus 710 provide communication into and out of thesystem 700; an input/output (I/O) device 770 and image sensor 610 aresuch communication devices. Other devices connected to the bus 710provide memory, for instance, a random access memory (RAM) 730 or aflash memory card 750. Lens 795 focuses an image on the pixel array ofimage sensor 610. It should be noted that the illustration of a camerais not intended to be limiting and that such an image sensor 610 couldbe included in any processor system including a scanner, machine vision,vehicle navigation, video phone, cell phone, personal digital assistant,surveillance system, auto focus system, star tracker system, motiondetection system, and other systems employing an image sensor.

The system 700 could alternatively be part of a larger processingsystem, such as a computer. Through the bus 710, the processor system700 illustratively communicates with other computer components,including but not limited to, a hard drive 740 and one or moreperipheral memory devices such as a floppy disk drive 780, a compactdisk (CD) drive 790.

The processes and devices described above illustrate methods and typicaldevices of many that could be used and produced. The above descriptionand drawings illustrate embodiments, which achieve contain objects,features, and advantages described herein as well as others. However, itis not intended that the embodiments be strictly limited to thosedescribed and illustrated. Any modifications, though presentlyunforeseeable, of the embodiments that come within the scope of thefollowing claims should be also considered.

1-13. (canceled)
 14. A method of forming a photosensor comprising thesteps of: providing a semiconductor substrate having a first doped layerof a first conductivity type; forming a second doped region of a secondconductivity type to define a photosensitive area above thesemiconductor substrate; forming at least one trench in the second dopedregion for redirecting reflected light from one portion of thephotosensitive region to another portion of the photosensitive region;and forming a third doped region of the first conductivity type over thesecond doped region.
 15. The method of claim 14, wherein the firstconductivity type is p-type and the second conductivity type is n-type.16. The method of claim 14, wherein the step of forming at least onetrench in the second doped region comprises forming at least oneu-shaped trench.
 17. The method of claim 14, wherein the step of formingat least one trench in the second doped region comprises forming atleast one v-shaped trench.
 18. The method of claim 14, wherein the stepof forming at least one trench in the second doped region furthercomprises forming a plurality of trenches. 19-23. (canceled)
 24. Amethod of forming an imaging device comprising: forming a raisedphotosensitive region completely above a top surface of a substrate; andforming a plurality of indentation features in the raised photosensitiveregion, where the plurality of indentation features are adapted toredirect reflected light from one portion of the raised photosensitiveregion to another portion of the raised photosensitive region.
 25. Themethod of claim 24, wherein the indentation features are formed having au-shaped configuration.
 26. The method of claim 24, wherein theindentation features are formed having downwardly extending sidewallsthat are capable of redirecting light.
 27. The method of claim 24,wherein the indentation features are formed having slanted sidewallsthat are capable of redirecting light.
 28. The method of claim 26,wherein the indentation features are formed having a rounded bottomcapable of redirecting light.
 29. The method of claim 24, wherein theformed raised photosensitive region comprises forming an upper electrodelayer above a hydrogenated amorphous silicon layer formed above a metalconductive layer, each layer being formed to contour to each of theplurality of indentation features of the raised photosensitive region.30. The method of claim 24, wherein each of the plurality of indentationfeatures are formed having an effective area determined by a particularlight wavelength.
 31. A method of forming an imaging pixel having araised photosensor, the method comprising: providing a substrate havinga first surface level; forming a first doped layer of a firstconductivity type in the substrate; forming a second doped layer of asecond conductivity type over the first doped layer at a second elevatedsurface level, the second doped layer having a plurality of indentationfeatures on an upper surface for redirecting light from one portion ofthe photosensitive region to another portion of the photosensitiveregion; and forming a third doped layer of a first conductivity type onthe upper surface of the plurality of indentation features.
 32. Themethod of claim 31, further comprising forming a color filter arraylayer above said third doped layer.
 33. The method of claim 32, furthercomprising forming a microlens layer above said color filter arraylayer.
 34. The method of claim 31, wherein the plurality of indentationfeatures are formed having curved sidewalls that are capable ofredirecting light.
 35. The method of claim 34, wherein the plurality ofindentation features are formed having u-shaped configurations.
 36. Themethod of claim 31, wherein the plurality of indentation features areformed having slanted sidewalls that are capable of redirecting light.37. The method of claim 36, wherein the plurality of indentationfeatures are formed having a v-shaped configuration.